1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of Related Art
A trench gate structure is generally known as a structure effective for refinement of a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field-Effect Transistor).
FIG. 9 is a schematic sectional view of a conventional semiconductor device 101 including a trench gate VDMOSFET.
This semiconductor device 101 includes an N+-type substrate 102. An N−-type epitaxial layer 103 is laminated on the N+-type substrate 102. An N−-type region 104 is formed on a base layer portion of the N−-type epitaxial layer 103, while a P−-type body region 105 is formed on a surface layer portion of the N−-type epitaxial layer 103 vertically adjacently to the N−-type region 104.
A trench 106 is formed by digging the N−-type epitaxial layer 103 from the surface thereof. The trench 106 passes through the P−-type body region 105, so that the deepest portion thereof reaches the N−-type region 104. Agate electrode 108 made of polysilicon doped with an N-type impurity in a high concentration is buried in the trench 106 through a gate insulating film 107.
An N+-type source region 109 is formed on a surface layer portion of the P−-type body region 105 along the trench 106. A P+-type source contact region 110 is formed in the N+-type source region 109 to pass through the N+-type source region 109.
An interlayer dielectric film 111 is laminated on the N−-type epitaxial layer 103. A source wire 112 is formed on the interlayer dielectric film 111. This source wire 112 is grounded. The source wire 112 is in contact (electrically connected) with the N+-type source region 109 and the P+-type source contact region 110 through a contact hole 113 formed in the interlayer dielectric film 111. A gate wire 114 is electrically connected to the gate electrode 108 through a contact hole (not shown) formed in the interlayer dielectric film 111.
A drain electrode 115 is formed on the back surface of the N+-type substrate 102.
A current can be flowed between the N+-type source region 109 and the drain electrode 115 by controlling the potential of the gate electrode 108 while applying a positive voltage of a proper level to the drain electrode 115 thereby forming a channel in the vicinity of the interface between the P−-type body region 105 and the gate insulating film 107.
The P−-type body region 105 is formed by implanting (ions of) a P-type impurity into the N−-type epitaxial layer 103 from the surface thereof and thereafter drive-in-diffusing the P-type impurity. Therefore, the P−-type body region 105 has an extremely low P-type impurity concentration in the vicinity of the interface between the same and the N−-type region 104. Thus, a depletion layer easily extends toward the N+-type source region 109, and hence the trench 106 must be deeply formed in order to prevent the so-called punch-through.
When the trench 106 is deeply formed, however, crystal defects resulting from remarkable stress may be caused around the upper and lower ends of the trench 106.